The present invention relates to clock signal wirings in a semiconductor integrated circuit or in a circuit formed on a wiring substrate and to technology for feeding clock signals, and further relates to technology that can be effectively adapted to computers that operate at high speeds in synchronism, for instance, with clock signals.
In a synchronous sequence circuit which is operated in synchronism with the clock signals, it is essential that the clock signals are distributed at the same timing to each of the portions of the circuit operated in synchronism. If there is deviation in timing among the portions of the circuit, the data are no longer transferred in correct sequence among these portions. The deviation in the timing, i.e., the deviation in phase of the clock signals supplied to each of the portions, is called clock skew.
In order to minimize the clock skew, the clock signals sent to each of the portions from the clock generating circuit or from the clock input circuit should be uniformly delayed. In the semiconductor integrated circuits which are highly densely integrated or which have logics of a large scale, however, it is not easy to decrease the clock skew due to undesired capacitances stemming from unequal clock wiring lengths and upper or lower crossing wiring layers caused by the arrangement of internal circuits and various internal signal wirings. In particular, when a design method is employed such as a gate array system or a standard cell system using an automatic wiring program, the width of the clock wirings is minimized like that of other signal wirings, and great difficulty is involved to estimate resistance components and capacitive components in the clock wirings.
So far, therefore, there has been proposed technology to equalize the capacitances of the wirings by partially expanding the wiring pattern from the clock distributing circuit to each of the portions or by connecting extra wirings as required as has been disclosed in Japanese Patent Laid-Open No. 254633/1985. As disclosed in Japanese Patent Laid-Open No. 78611/1988, furthermore, there has been proposed technology to adjust the addition of wirings by inserting additional gates to those wirings that have short clock arrival times.